VMM Vs UVM
VMM and UVM are two major verification methodologies that are built on SystemVerilog based test benches. VMM stands for Verification Methodology Manual and UVM stands for Universal Verification Methodology. The industry is shifting gears towards UVM due to the flexibility and powerful register model. The differences and the similarities are highlighted in this article to briefly understand the details.
UVM has phasing similar to VMM. Although the names of the phases are different, and the behavior obviously has minor differences, there is not a whole leap of difference here. The idea is to separate out elaboration from stimulus generation in a test in both the cases. The subtle difference again, starts to appear in the part division of the phases. Another difference is the control in the hands of the developer, where user-defined phasing and user-defined relationships between the phases is a magic wand in hand, to control the stimulus better.
Register model –
The register model is the real takeaway in UVM. A methodology becomes powerful when it enables the abstraction of chunks of memory such as registers. The backbone of the register model comes from Memory Allocation Manager (MAM) in VMM. Now the area where UVM differs is the granularity it provides to the developer. That is, the developer I sable to iterate through hundreds of registers/memory blocks and memory maps, with a single register model per module. The surprise does not end there. The RM provides bit level access, and control for each of the memory sub-blocks. Chunks of memory blocks can be read and written from within a test stimulus in no time. The VMM MVM model only enables the offset and byte level access.
Sequences Vs Scenarios –
Both UVM sequences and VMM scenarios have the same capabilities. They need to be able to allow multi-layered stimulus and modularity of tests. The beauty of these components lies in separating the stimulus from the testbench which is a head-on challenge for every verification engineer. The differences that sequences provide are the pronounced object oriented approach in terms of virtual sequences.
These are some of the major differences existing today. The purpose of the article is to take up same/similar components and concepts to see how differently the two methodologies empower the verification engineer.